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1 flc series white electronic designs one research drive westborough , ma 01581 http://www. whiteedc .com pc card products july 28. 1999 features ? low cost medium/high density linear flash card ? based on amd am29f040 components (equivalent of amd?s amc0xxcflka) ? single supply operation, no additional programming voltage required - 5 v only for write, erase and read operations ? fast read performance - 150ns maximum access time ? pcmcia/jeida 68-pin standard - x8/ x16 data interface - type i form factor ? automated write and erase operations - 64kbyte memory sectors for faster automated erase speed - typically 1.5 s per single memory sector erase - random address writes to previously erased bytes; 16s per byte typical ? 100,000 erase/program cycles wedc?s flc series flash memory cards offer medium/high density linear flash solid state storage solutions for code and data storage, high performance disk emulation and execute in place (xip) applications in mobile pc and dedicated (embedded) equipment. flc series cards conform to pcmcia international standard. the card?s control logic provides the system interface and controls the internal flash memories. card can be read/written in byte-wide or word-wide mode which allows for flexible integration into various systems. combined with file management software, such as flash translation layer (ftl), flc flash cards provide removable high-performance disk emulation. the flc series cards contain separate 2kb eeprom memory for card information structure (cis) which can be used for easy identification of card characteristics. the wedc flc series is based on amd am29f040 flash memories; the flc04 is a direct equivalent of amd?s amc0xxcflka, however it offers wider range of intermediate memory capacities. note: standard options include attribute memory. cards without attribute memory are available. cards are also available with or without a hardware write protect switch. pcmcia flash memory card 1 megabyte through 10 megabyte (amd based) pcmcia flash memory card flc series flc series cards are based on the am29f040 (4mb) components which work with single 5v applications. manufacture/device code is 01h/a4h. flc series is designed to support from 2 to 20components, providing densities ranging from 1mb to 10mb in 1mb increments. in support of the pc card 95 standard for word wide access devices are paired. write, read and erase operations can be performed as either a word or byte wide operation . by multiplexing a0, ce1# and ce2#, 8-bit hosts can access all data on data lines dq0 - dq7. the flc series cards conform to the pc card standard (pcmcia) and jeida, providing electrical and physical compatibility. the pc card form factor offers an industry standard pinout and mechanical outline, allowing density upgrades without system design changes. wedc?s standard cards are shipped with wedc?s logo. cards are also available with blank housings (no logo). the blank housings are available in both a recessed (for label) and flat housing. please contact wedc sales representative for further information on custom artwork. general description architecture overview preliminary
2 flc series white electronic designs one research drive westborough , ma 01581 http://www. whiteedc .com pc card products july 28. 1999 data bus d8-d15 vcc device 18 device 1 csl9 device 2 csl1 csl0 device pair 0 device pair 1 device 3 device pair 9 data bus q0-q7 i/o buffer control vcc data bus d0-d7 device 19 data bus q8-q15 device 0 q0-q7 wr# csl9 rd# c9 att enable csl0 c0 control logic pcmcia interface ctrl attrib . mem cis eeprom 2kb we# oe# ce2# ce1# reg# a0 wp address bus control address bus address buffer array address bus a1-a23 block diagram device type manuf id device id am29f040 01 h a4 h a1-a19 low high csh9 c9 csh0 c0 csh9 csh1 csh0 vcc vcc supported components (max 20 x): am29f040 bvd1 bvd2 vs1 vs2 open open vcc cd1# cd2# gnd vcc wait# vpp1 vpp2 open open
3 flc series white electronic designs one research drive westborough , ma 01581 http://www. whiteedc .com pc card products july 28. 1999 pinout notes: 1) wait#, bvd1 and bvd2 are driven high for compatibility 2) shows density for which specified address bit is msb. higher order address bits are n.c. (i.e. 4mb a21 is msb a22 - a25 are nc). 3) for the 3mb card the memory will wrap at the 4mb boundary, for 5mb, 6mb, and & 7mb cards the memory will wrap at the 8mb boundary, for 9mb and 10mb cards the memory will wrap at the 16mb boundary. mechanical 54.0mm 0.10 (2.126?) 10.0mm min (0.400?) 1.6mm 0.05 (0.063?) 1.0mm 0.05 (0.039?) 1.0mm 0.05 (0.039?) 3.3mm t1 (0.130?) t1=0.10mm interconnect area t1=0.20mm substrate area interconnect area 10.0mm min (0.400?) 3.0mm min 85.6mm 0.20 (3.370?) substrate area pin signal name i/o function active pin signal name i/o function active 1 gnd ground 35 gnd ground 2 dq3 i/o data bit 3 36 cd1# o card detect 1 low 3 dq4 i/o data bit 4 37 dq11 i/o data bit 11 4 dq5 i/o data bit 5 38 dq12 i/o data bit 12 5 dq6 i/o data bit 6 39 dq13 i/o data bit 13 6 dq7 i/o data bit 7 40 dq14 i/o data bit 14 7 ce1# i card enable 1 low 41 dq15 i data bit 15 8 a10 i address bit 10 42 ce2# i card enable 2 low 9 oe# i output enable low 43 vs1 o voltage sense 1 n.c. 10 a11 i address bit 11 44 rfu reserved n.c. 11 a9 i address bit 9 45 rfu reserved n.c. 12 a8 i address bit 8 46 a17 i address bit 17 13 a13 i address bit 13 47 a18 i address bit 18 14 a14 i address bit 14 48 a19 i address bit 19 1mb(2) 15 we# i write enable low 49 a20 i address bit 20 2mb(2) 16 rdy/bsy # o ready/busy n.c. 50 a21 i address bit 21 4mb(2,3) 17 vcc supply voltage 51 vcc supply voltage 18 vpp1 prog. voltage n.c. 52 vpp2 prog. voltage n.c. 19 a16 i address bit 16 53 a22 i address bit 22 8mb(2,3) 20 a15 i address bit 15 54 a23 i address bit 23 16/10mb(2,3) 21 a12 i address bit 12 55 a24 i address bit 24 n.c. 22 a7 i address bit 7 56 a25 i address bit 25 n.c. 23 a6 i address bit 6 57 vs2 o voltage sense 2 n.c. 24 a5 i address bit 5 58 rst i card reset n.c. 25 a4 i address bit 4 59 wait# o extended bus cycle low(1) 26 a3 i address bit 3 60 rfu reserved n.c. 27 a2 i address bit 2 61 reg# i attrib mem select low 28 a1 i address bit 1 62 bvd2 o bat. volt. detect 2 (1) 29 a0 i address bit 0 63 bvd1 o bat. volt. detect 1 (1) 30 dq0 i/o data bit 0 64 dq8 i/o data bit 8 31 dq1 i/o data bit 1 65 dq9 i/o data bit 9 32 dq2 i/o data bit 2 66 dq10 o data bit 10 33 wp o write potect high 67 cd2# o card detect 2 low 34 gnd ground 68 gnd ground
4 flc series white electronic designs one research drive westborough , ma 01581 http://www. whiteedc .com pc card products july 28. 1999 symbol type name and function a0 - a25 input address inputs: a0 through a25 enable direct addressing of up to 64mb of memory on the card. signal a0 is not used in word access mode. the memory will wrap at the card density boundary (see pinout, note 3). the system should not try to access memory beyond the card density. a25 is the most significant bit. a24 ? a25 are not connected. dq0 - dq15 input/output data input/output: dq0 through dq15 constitute the bi-directional databus. dq0 ? dq7 constitute the lower (even) byte and dq8 ? dq15 the upper (odd) byte. dq15 is the msb. ce1#, ce2# input card enable 1 and 2: ce1# enables even byte accesses, ce2# enables odd byte accesses. multiplexing a0, ce1# and ce2# allows 8-bit hosts to access all data on dq0 - dq7. oe# input output enable: active low signal gating read data from the memory card. we# input write enable: active low signal gating write data to the memory card. rdy/bsy# n.c. ready/busy output: indicates status of internally timed erase or program algorithms. this signal is not connected. cd1#, cd2# output card detect 1 and 2: provide card insertion detection. these signals are internally connected to ground on the card. the host shall monitor these signals to detect card insertion (pulled-up on host side). wp output write protect: write protect reflects the status of the write protect switch on the memory card. wp set to high = write protected, providing internal hardware write lockout to the flash array. if card does not include optional write protect switch, this signal will be pulled low internally indicating write protect = "off". vpp1 n.c. program/erase power supply: provides programming voltages 12.0v for lower byte (d0 ? d7) memory components. this signal is not connected. vpp2 n.c. program/erase power supply: provides programming voltages 12.0v for upper byte (d8 ? d15) memory components. this signal is not connected. vcc card power supply: (5.0v). gnd card ground reg# input attribute memory select : active low signal, enables access to attribute memory plane, occupied by card information structure and card registers. rst n.c. reset: active high signal for placing cards in power-on default state. this signal is not connected. wait# output wait: this signal is pulled high internally for compatibility. no wait states are generated. bvd1, bvd2 output battery voltage detect: these signals are pulled high to maintain sram card compatibility. vs1, vs2 output voltage sense: notifies the host socket of the card's vcc requirements. vs1 and vs2 are open to indicate a 5v card. rfu reserved for future use n.c. no internal connection to card: pin may be driven or left floating card signal description read function common memory attribute memory function mode /ce2 /ce1 a0 /oe /we /reg d15-d8 d7-d0 /reg d15-d8 d7-d0 standby mode h h x x x x high-z high-z x high-z high-z byte access (8 bits) h l l l h h high-z even-byte l high-z even-byte h l h l h h high-z odd-byte l high-z not valid word access (16 bits) l l x l h h odd-byte even-byte l not valid even-byte odd-byte only access l h x l h h odd-byte high-z l not valid high-z write function standby mode h h x x x x x x x x x byte access (8 bits) h l l h l h x even-byte l x even-byte h l h h l h x odd-byte l x x word access (16 bits) l l x h l h odd-byte even-byte l x even-byte odd-byte only access l h x h l h odd-byte x l x x functional truth table
5 flc series white electronic designs one research drive westborough , ma 01581 http://www. whiteedc .com pc card products july 28. 1999 absolute maximum ratings (1) operating temperature ta (ambient) commercial 0c to +60 c industrial -40c to +85 c storage temperature commercial -30c to +80 c industrial -40c to +85 c voltage on any pin relative to vss -0.5v to vcc+0.5v vcc supply voltage relative to vss -0.5v to +7.0v notes: (1) stress greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. symbol parameter density notes typ (2) max units test conditions i ccr vcc read current all 45 ma vcc = vccmax tcycle = 150ns,cmos levels i ccw vcc program current all 65 ma programming in progress i cce vcc erase current all 65 ma erasure in progress 1mb 0.015 0.7 2mb 0.015 0.9 4mb 0.015 1.3 i ccs ( cmos) vcc standby current 10mb 0.015 2.5 ma vcc = vccmax control signals = vcc cmos levels notes: 1. all currents are rms values unless otherwise specified. iccr, iccw and icce are based on byte wide operations. for 16 bit operation values are double. 2. typical: vcc = 5v, t = +25oc cmos test conditions: vcc = 5v 5%, vil = vss 0.2v, vih = vcc 0.2v dc characteristics (1) symbol parameter notes min max units test conditions i li input leakage current 1 20 a vcc = vccmax vin =vcc or vss i lo output leakage current 1 20 a vcc = vccmax vout =vcc or vss v il input low voltage 1 0 0.8 v v ih input high voltage 1 0.7vcc vcc+0.5 v v ol output low voltage 1 0.4 v iol = 3.2ma v oh output high voltage 1 vcc-0.4 vcc v ioh = -2.0ma v lko vcc erase/program lock voltage 1 3.2 4.2 v notes: 1) values are the same for byte and word wide modes for all card densities. 2) exceptions: leakage currents on ce1#, ce2#, oe#, reg# and we# will be < 500 a when vin = gnd due to internal pull-up resistors.
6 flc series white electronic designs one research drive westborough , ma 01581 http://www. whiteedc .com pc card products july 28. 1999 150ns symbol (pcmcia) parameter min max unit t rc read cycle time 150 ns t a (a) address access time 150 ns t a (ce) card enable access time 150 ns t a (oe) output enable access time 75 ns t su (a) address setup time 20 ns t su (ce) card enable setup time 0 ns t h (a) address hold time 20 ns t h (ce) card enable hold time 20 ns t v (a) output hold from address change 0 ns t dis (ce) output disable time from ce# 75 ns t dis (oe) output disable time from oe# 75 ns t en (ce) output enable time from ce# 5 ns t en (oe) output enable time from oe# 5 ns ac characteristics notes: 1. ac timing diagrams and characteristics are guaranteed to meet or exceed pcmcia 2.1 specifications read timing diagram note 1 note 1 a[25::0], /reg /ce1, /ce2 /oe d[15::0] tc(r) ta(a) th(a) tv(a) ta(ce) tsu(ce) th(ce) ten(oe) ta(oe) tsu(a) data valid tdis(ce) tdis(oe) read timing parameters note 1: signal may be high or low in this area
7 flc series white electronic designs one research drive westborough , ma 01581 http://www. whiteedc .com pc card products july 28. 1999 150ns symbol (pcmcia) parameter min max unit t c w write cycle time 150 ns t w (we) write pulse width 80 ns t su (a) address setup time 20 ns t su (a-weh) address setup time for we# 100 ns t su (ce- weh) card enable setup time for we# 100 ns t su (d-weh) data setup time for we# 50 ns t h (d) data hold time 20 ns t rec (we) write recover time 20 ns t dis (we) output disable time from we# 75 ns t dis (oe) output disable time from oe# 75 ns t en (we) output enable time from we# 5 ns t dis (oe) output enable time from oe# 5 ns t su (oe-we) output enable setup from we# 10 ns t h (oe-we) output enable hold from we# 10 ns t su (ce) card enable setup time from oe# 0 ns t h (ce) card enable hold time 20 ns notes: 1. ac timing diagrams and characteristics are guaranteed to meet or exceed pcmcia 2.1 specifications write timing diagram write timing parameters th(oe-we) note 1 /ce1, /ce2 note 1 tsu(ce-weh) tc(w) a[25::0], /reg tw(we) tdis(we) th(d) d[15::0](din) data input tsu(a) tsu(a-weh) /oe tsu(ce) tsu(d-weh) trec(we) th(ce) tsu(oe-we) tdis(oe) d[15::0]( dout) ten(oe) ten(we) note 2 note 2 /we notes: 1)signal may be high or low in this area 2)when the data i/o pins are in the output state, no signals shall be applied to the data pins (d15 - d0) by the host system.
8 flc series white electronic designs one research drive westborough , ma 01581 http://www. whiteedc .com pc card products july 28. 1999 parameter comments min typ (1) max units sector erase time excludes 00h programming prior to erasure 1.0 15 s chip erase time excludes 00h programming prior to erasure 8 120 s byte programming time excludes system-level overhead 7 1000 (3) s chip programming time excludes system-level overhead 3.6 25 (3, 4) s data write and erase performance notes: 1. typical: nominal voltages, t a = 25oc, 100,000 cycles 2. although embedded algorithms allow for a longer chip program and erase time, the actual time will be considerably less since bytes program or erase significantly faster than the worst case byte. 3. under worst case condition of 90c, 4.5 v vcc , 100,000 cycles. 4. the embedded algorithms allow for 2.5 ms byte program time. dq5 = ?1? only after a byte takes the theoretical maximum time to program. a minimal number of bytes may require significantly more programming pulses than the typical byte. the majority of the bytes will program within one or two pulses. this is demonstrated by the typical and maximum programming times. vcc = 5v 5%, t a = 25oc
9 flc series white electronic designs one research drive westborough , ma 01581 http://www. whiteedc .com pc card products july 28. 1999 cis information for flc series cards address value description address value description 00h 01h cistpl_device 3eh 01h tpllv1_minor 02h 03h tpl_link 40h 45h e 04h 53h flash = 150ns (device writable) 42h 44h d 06h 0dh card size:1mb 44h 49h i 06h 2mb 46h 37h 7 2dh 3mb 48h 50h p 0eh 4mb 4ah 30h 1) 0 4dh 5mb 4ch 30h 1) 0 16h 6mb 4eh 31h 1) 1 6dh 7mb 50h 46h f 1eh 8mb 52h 4ch l 8dh 9mb 54h 43h c 26h 10mb 56h 30h 2) 0 08h ffh end of device 58h 32h 2) 2 0ah 18h cistpl_jedec_c 5ah 2dh - 0ch 02h tpl_link 5ch 2dh - 0eh 01h amd - id 5eh 2dh - 10h a4h am29f040- id 62h 31h 1 12h 17h cistpl_device_a 64h 35h 5 14h 03h tpl_link 66h 20h space 16h 42h eeprom - 200ns 68h 00h end text 18h 01h device size = 2kbytes 6ah 43h c 1ah ffh end of tuple 6ch 4fh o 1ch 1eh cistpl_devicegeo 6eh 50h p 1eh 06h tpl_link 70h 59h y 20h 02h dgtpl_bus 72h 52h r 22h 11h dgtpl_ebs 74h 49h i 24h 01h dgtpl_rbs 76h 47h g 26h 01h dgtpl_wbs 78h 48h h 28h 01h dgtpl_part 7ah 54h t 2ah 01h flash device 7ch 20h space non-interleaved 7eh 45h e 2ch 20h cistpl_manfid 80h 4ch l 2eh 04h tpl_link(04h) 82h 45h e 30h f6h edi tplmid_manf: lsb 84h 43h c 32h 01h edi tplmid_manf: msb 86h 54h t 34h 00h lsb: number not assigned 88h 52h r 36h 00h msb: number not assigned 8ah 4fh o 38h 15h cistpl_vers1 8ch 4eh n 3ah 47h tpl_link 8eh 49h i 3ch 04h tpllv1_major 90h 43h c 1) address value desc . value desc . value desc . value desc . value desc . value desc . value desc . value desc . value desc . 4ah 30h 0 30h 0 30h 0 30h 0 30h 0 30h 0 30h 0 30h 0 30h 0 4ch 30h 0 30h 0 30h 0 30h 0 30h 0 30h 0 30h 0 30h 0 31h 1 4eh 32h 2 33h 3 34h 4 35h 5 36h 6 37h 7 38h 8 39h 9 30h 0 2) address value description 56h 30h 0 58h 34h 4
10 flc series white electronic designs one research drive westborough , ma 01581 http://www. whiteedc .com pc card products july 28. 1999 cis information for flc series cards - contd. 92h 20h space 94h 44h d 96h 45h e 98h 53h s 9ah 49h i 9ch 47h g 9eh 4eh n a0h 53h s a2h 20h space a4h 49h i a6h 4eh n a8h 43h c aah 4fh o ach 52h r aeh 50h p b0h 4fh o b2h 52h r b4h 41h a b6h 54h t b8h 45h e bah 44h d bch 20h space beh 00h end text c0h 31h 1 c2h 39h 9 c4h 39h 9 c6h 37h 7 c8h 00h end text cah 00h end of list cch ffh cistpl_end
11 flc series white electronic designs one research drive westborough , ma 01581 http://www. whiteedc .com pc card products july 28. 1999 ordering information edi 7p xxx flc yy ss t zz based on am29f040 where xxx: 001 1mb 002 2mb 003 3mb 004 4mb 005 5mb 006 6mb 007 7mb 008 8mb 009 9mb 010 10mb yy: 01 no attribute memory, no write protect switch 02 attribute memory, no write protect switch 03 no attribute memory, with write protect switch 04 attribute memory, with write protect switch ss: 00 wedc silkscreen 01 blank housing, type i 02 blank housing, type i recessed t: c commercial i ** industrial zz: 15 150ns note: options without attribute memory and with/without hardware write protect switch are available. ** denotes advanced information date of revision revision description 23-dec-98 0 initial release 28-jul-99 1 logo change revision history white electronic designs, corp one research drive, westborough , ma 01581, usa tel : (508) 366 5151 fax: (508) 836 4850 www. whiteedc .com

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